23-26 March, 1998, Kona, Hawaii Domenico Bonaccini, Robert K. Tyson Alan F. M. Moorwood, Masanori Iye ... architecture used for the IRST application described in this paper is the Mercury RACEwayAr architecture utilizing the Intel ... The computational units take three clocks for a single 32-bit floating point output, but are pipelined to produce an output on every clock cycle. ... This provides 160 megabytes per second processing input, four times the bandwidth of the 64-bit external.
|Title||:||Adaptive Optical System Technologies|
|Author||:||Domenico Bonaccini, Robert K. Tyson|
|Publisher||:||Society of Photo Optical - 2004|