*Covers design, packaging, construction, assembly, and application of all three approaches to Area Array Packaging: Ball Grid Array (BGA), Chip Scale Package (CSP), and Flip Chip (FC) *Details the pros and cons of each technology with varying applications *Examines packaging ramifications of high density interconnects (HDI)The driver for the development of this technology was the need for enough wiring and interconnection to support high-performance components ... A schematic of a multilayer PWB is shown in Fig. ... The lamination is a sequential process (i.e., the layers are laminated one at a time versus one grand lamination at the end). 4.
|Title||:||Area array packaging handbook|
|Publisher||:||McGraw-Hill Professional - 2002|