qIn the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process.q qThis book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics.q--BOOK JACKET.On the other hand, a new wire (the global bit-line) and a number of bypass switches are introduced in the design. ... (only one bypass switch per segment as opposed to a pass transistor per cell) that smaller prechargers/drivers and smaller sense amps can be used. ... Figure 4.23 depicts a simplified block diagram of a 4-way set associative cache. ... in how the tags and data arrays are combined or divided in sub-banks (e.g., the way CACTI Step 1 DATA DATA DATA DATA Step 2 Stepanbsp;...
|Title||:||Computer Architecture Techniques for Power-efficiency|
|Author||:||Stefanos Kaxiras, Margaret Martonosi|
|Publisher||:||Morgan & Claypool Publishers - 2008|