Finally, the work concludes with a summary of the design of a 6.25-Gb/s serial I/O transceiver for backplane communications that implements error correction coding to reduce equalization power and transmitter output swing. The design of the transmit driver with pre-emphasis equalization, receiver amplifier, and voltage controlled oscillator is described. The I/O transceiver is fully ESD-protected with an expected 2-kV human body model failure threshold.Therefore, from Figures 2.30 and 2.31, WN = 0.5 um and WP = 1.0 um present the best tradeoff in terms of optimizing the FOMs. ... As was inferred from the 1 80- nm study and shown in Figures 2.32 and 2.33, parallel routing exhibits significant benefits over ... the parallel routing scheme reduces the parasitic series resistance of the interconnect, providing an evenly distributed current flow across the diode.
|Title||:||Design and ESD Protection of Wideband, Radio Frequency Integrated Circuits in CMOS Technologies|
|Author||:||Karan Singh Bhatia|
|Publisher||:||ProQuest - 2008|