IEEE VLSI Test Symposium

IEEE VLSI Test Symposium

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Generic SerDes block diagram Figure 1 illustrates a block diagram for a generic, single-channel SerDes device. ... PRBS / Compliancea#39; Pattern Generator Parallel Ar a–i Transmit I JXTi Data 1 Parallel _ Transmit Clk Low-Speed Ref Clk a#39; Parallel Rev Clk ransmit| FIFO ... Prior to catastrophic transistor or circuit failures such as gate oxide shorts, these effects modify turn-on and gain characteristics, biasing, anbsp;...

Title:IEEE VLSI Test Symposium
Publisher: - 2005


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