The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.MUSTANG: State assignment of finite state machines targeting multilevel logic implementations. ... Xilinx inc, 2000 FPGA Compiler II / FPGA Express VHDL Reference Manual, Version 1999.05, Synopsys, Inc., May 1999 Bob Lisanke.
|Title||:||Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation|
|Author||:||Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido|
|Publisher||:||Springer - 2003-08-02|