... Synthesis for Silicon Compilers held in Grenoble, France, 25-27 May, 1988 GabriAule Saucier Paul Michael McLellan ... Figure 10(c) : Compared to the first solution, the multiplications can also be speeded up by using several ALUa#39;s. In this example, all operations belonging the first biquad are assigned manually to ALU 1, the second biquad to ALU 2, and the first order section to ALU 3. ... Alternatively, several other parts of the DSP-system may be integrated on the same processor.
|Title||:||Logic and architecture synthesis for silicon compilers|
|Publisher||:||North Holland - 1989-04|