Low Voltage, Low Power VLSI Subsystems

Low Voltage, Low Power VLSI Subsystems

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This monograph details cutting-edge design techniques for the low power circuitry required by the many new miniaturized business and consumer products driving the electronics market This book teaches cutting edge techniques in low power CMOS/BICMOS VLSI subsystems design, covering in depth the challenges facing integrated circuit and system designers in creating low-power VLSI subsystems. Leakage currents and noise coupling in high-speed dynamic circuits and systems will be discussed, along with new circuit techniques to overcome basic design obstacles.On the other hand, if HVGE is asserted high, the output signal is sampled and the circuit consumes a dc current for a short period of time. ... A clock signal, clk, is applied to the interconnection node, A, which oscillates between Vth and (Vaquot;th - VDD)- The clk ... Figure 7.1 9 Schematic diagram of the two-phase VgB charge.

Title:Low Voltage, Low Power VLSI Subsystems
Author:Kiat Seng Yeo, Kaushik Roy
Publisher:McGraw Hill Professional - 2005


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