Parallel Methods for VLSI Layout Design

Parallel Methods for VLSI Layout Design

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Node 12, which corresponds to column 9, must examine the columns in region 3, i.e., columns to the right of column 9. Column 10 happens ... Figure 9.16 shows how three processors can be used to process the AND/OR tree of the example. The work done by ... on. a. Hypercube. Brouwer and Banerjee [BB88] applied simulated annealing to the problem of two-layer channel routing. A well known lower bound on the number of tracks required to route a channel is the channel density.

Title:Parallel Methods for VLSI Layout Design
Author:Si. Pi Ravikumār
Publisher:Greenwood Publishing Group - 1996


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