Proceedings of ASP-DAC/VLSI Design 2002

Proceedings of ASP-DAC/VLSI Design 2002

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Papers from a January 2002 conference are organized into four sessions each on low power design, synthesis, testing, layout, and interconnects and technology, as well as two sessions each on embedded systems, verification, and VLSI architecture, one session on analog design, and one session on hot cWe added a coprocessor pipeline in the MIPS R10K which supports vector integer multiplication. ... The fetch unit fetches 8 instructions per cycle and decode unit decodes 3 instructions per cycle, hence there is a potential for instruction loss.

Title:Proceedings of ASP-DAC/VLSI Design 2002
Publisher:IEEE - 2002-01


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