The standard parallel computer implementation of the test-and-set instruction generates a read-modify-write operation between processing element and the shared memory. That is, a special bus read operation is generated that locks the anbsp;...
|Title||:||The Cache-coherence problem in shared-memory multiprocessors|
|Author||:||Milo Tomašević, Veljko Milutinović|
|Publisher||:||IEEE Computer Society - 1993-06|